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| Features * * * * Links an Embedded ARM7TDMITM Core to the Atmel AMBATM Bus Bus Master Granted State Machine Bus Interface State Machine Fully Scan Testable (up to 96% Fault Coverage) Description Designed for the Atmel implementation of the AMBA Bus, the ARM7TDMI Bus Interface module enables an ARM7TDMI embedded core to become an AMBA bus master. The bus interface is designed to link the embedded ARM7TDMI core signals to the AMBA Bus. It includes two state machines. The first state machine determines if the master is currently granted the bus, and the second, more complex, state machine is used to control the bus interface of the master. This peripheral can only be used with an embedded ARM7TDMI core. There are no user-programmable registers in this block. Figure 1. ARM7TDMI Bus Interface Pin Configuration nreset_r nreset_f system clock system clock_n AMBA Bus Inputs bwait_in berror_in blast_in agnt AMBA Wrapper (ARM7TDMI Interface) nwait abort nmreq seq nopc ntrans ARM7TDMI AMBA Related Signals ARM7TDMITM Bus Interface 32-bit Embedded Core Interface btran1:0] AMBA Bus Outputs bprot1:0] mabe scan_test_mode test_se Scan Interface test_so test_si Rev. 1283B-05/00 1 Table 1. Bus Interface Pin Description Name Direction Source/Destination Description AMBA Bus Inputs nreset_r nreset_f clock nclock bwait_in berror_in blast_in agnt Input Input Input Input Input Input Input Input Reset Controller Reset Controller System reset for flip-flop working on the rising edge of the System Clock (nreset_r synchronous to nclock). Active low. System reset for flip-flop working on the rising edge of the inverted System Clock (nreset_f synchronous to clock). Active low. System Clock Inverted System Clock Multiplexed BWAIT response from all the peripherals. Active high. Multiplexed BERROR response from all the peripherals. Active high. Multiplexed BLAST response from all the peripherals. Active high. Bus Grant: indicates that the bus master (ARM7TDMI) will be granted the bus when BWAIT is low. AMBA Bus Outputs btran[1:0] Output Current bus master/decoder, slaves Transfer type: type of the next transaction (Address-only, Nonsequential or Sequential). To be connected to the tri-state bus BTRAN[1:0] of the ASB. Protection control: indicates if the transfer is an opcode fetch or data access, as well as if the transfer is a supervisor mode access or a user mode access. To be connected to the tri-state bus BPROT[1:0] of the ASB. Master address bus enable: indicates when BA bus can be taken into account. Active high. Not wait: used when accessing slow peripherals to make the processor wait. Active Low. Memory abort: tells the processor that a requested access is not allowed. Active High. Not memory request: memory access requested by the processor. Active Low. Sequential address: next address (memory access) will be related to the last memory access. Active High. Not op-code fetch: indicates that the processor is fetching an instruction from the memory. Active Low. Not memory translate: indicates that the processor is in user mode. Active Low. Scan Test scan_test_mode Input Must be tied to 1 during scan test Must be tied to 0 in functional mode Test scan shift enabled when tied to 1 Test scan input (input of the scan chain) Test scan output (output of the scan chain) Slaves + decoder Slaves + decoder Slaves + decoder Arbiter bprot[1:0] Output Current bus master mabe Output ARM7TDMI AMBA Related Signals nwait abort nMREQ seq nopc ntrans Output Output Input Input Input Input ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI ARM7TDMI test_se Input Input test_si(1) Output test_so(1) Note: 1. The scan chain uses the clock BCLK. Scan Test Configuration The coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs can be observed. In order to achieve this, the ATPG vectors must be generated on the entire circuit (top level) which includes the ARM7TDMI Bus Interface or all ARM7TDMI Bus Interface I/Os must have a top level access and ATPG vectors must be applied to these pins. 2 Bus Interface Bus Interface Operating in an AMBA Bus System Figure 2. An Example of ARM7TDMI Core and Bus Interface Implementation "1" bigend cpa cpb dbgen extern0 extern1 isync sdoutbs bl[3:0] dbe busen abe ale ape tbe nenin "0" breakpt dbgrq brdata[31:0] core_clock nreset_f bwrite ntrst tck tdi tms breakpt dbgrq din[31:0] mclk nreset nrw ntrst tck tdi tms nwait abort nmreq seq nopc ntrans ARM7TDMI Core a[31:0] commrx commtx dbgack dout[31:0] eclk lock mas[1:0] nexec nfiq nirq nm[4:0] ntdoen tapsm[3:0] tbit tdo ba[31:0] commrx commtx dbgack bwdata[31:0] eclk block bsize[1:0] nexec nfiq nirq nm[3:0] ntdoen tapsm[3:0] tbit tdo nwait wrapper_clock wrapper_clock_n nreset_r scan_test_mode clock nclock nreset_r nreset_f scan_test_mode bwait_in abort nmreq seq nopc ntrans ARM7TDMI Bus Interface blast_in berror_in agnt btran[1:0] bprot[1:0] mabe bwait blast berror agnt btran[1:0] bprot[1:0] mabe 3 Figure 3. Data Buses pdc_sel_bridge Read Data Manager ARM Memory Controller (Including Decoder, EBI and ARAM Controller) ARM7TDMI Core and Wrapper dsel_bridge brdata (DIN on ARM Core) BDout bwait_from_APB wait_1C APB Peripherals BD_from_APB BD_from_masters Bridge bwait_to_ASB areq agnt bwait_in (DOUT on ARM Core) bwdata bridge_sel data_to_master pdc_data Master Signals Manager data_from_masters bwait_in bwdata bwait Arbiter (N masters) agnt[i] areq[i] agnt[N-1] areq[N-1] brdata Master[i] agnt areq Advanced System Bus (ASB) Advanced Peripheral Bus (APB) 4 Bus Interface Bus Interface Figure 4. Master Control Signals ARM Memory Controller Including Decoder, EBI and ARAM Controller) ARM7TDMI Core and Wrapper bwrite mabe ba blok bprot bsize btran bwrite 2 btran[1:0] bsize ba BusEnable_(N-1) ba_(N-1) Master Signals Manager APB Peripherals bprot_(N-1) 2 bwriteout 2 agnt[N-1] 2 bsize_(N-1) btran_(N-1) bwrite_(N-1) bwrite_(i) write_ master 2 Not Used in this Configuration btranout bsizeout bprotout baout address 2 2 2 btran_(i) bsize_(i) bprot_(i) Bridge ba_(i) BusEnable_(i) agnt[i] agnt[N-1] bwrite btran bsize bprot blok ba BusEnable blok[N-1:0] Arbiter (N masters) agnt areq Master agnt[i] areq[i] agnt[N-1] areq[N-1] 5 Bus Master Interface Description The bus master interface consists of a state machine that is used to determine if the master is currently granted the bus, and to control the bus interface of the master. Bus Interface State Machine The main bus interface state machine is falling edge triggered and contains six states. The entire state diagram, as shown in Figure 6, is quite complex but can be considered in four quadrants: Granted State Machine The granted state machine is used to determine whether or not the bus master has been granted the bus. It runs on the rising edge of the system clock and has only two states GRANTED and NOT_GRANTED. The state diagram is shown below. Figure 5. Bus Master Granted State Machine BWAIT + !AGNT BWAIT + AGNT No Transfer Request Not Granted Transfer Request Not Granted No Transfer Request Granted Transfer Request Granted NOT_GRANTED Granted = 0 !BWAIT & AGNT !BWAIT & !AGNT GRANTED Granted = 1 The "Transfer Request, Granted" quadrant contains three states, which handle bus turn around and the retract operation. The two internal bus master signals Granted and Request control the majority of the transitions around the state diagram. Granted is generated from the simpler state machine described above and Request is generated directly by the bus master. Request is asserted high when the bus master requires a transfer on the bus and is low when the bus master does not need access to the bus. The only time when a transition around the state diagram is not controlled by Granted and Request is when the bus master is in the ACTIVE state. In this state the transition to the next state is determined by the transfer response that is received. WAIT, DONE, LAST, ERROR and RETNEXT shown in the diagram correspond to the encoding of the transfer response signals. The output from the state machine is the internal Granted signal, which is used in the main bus master state machine. It is important to note that the agnt signal may be asserted for a number of clock cycles, but it is only when agnt is asserted and bwait is low that the bus master actually becomes GRANTED. An important design consideration is that the state machine may be asynchronously reset into either state depending on the value of the agnt signal. During reset one bus master in the system is set as the default bus master, as indicated by agnt being asserted during reset, and will be reset in to the GRANTED state. All other bus masters will be reset into the NOT_GRANTED state. 6 Bus Interface Bus Interface Figure 6. Bus Master Main State Machine No Transfer Request Not Granted !Granted & !Request !Granted & Request IDLE Granted & Request Granted Granted & !Request HOLD Transfer Request Not Granted !Granted !Granted !Granted !Granted & Request Granted !Granted & !Request Granted & Request BUSIDLE WAIT RETNEXT RETRACT ACTIVE Granted & !Request Granted & !Request DONE+ LAST+ ERROR Granted & Request !Granted & !Request !Granted & Request No Transfer Request Granted Transfer Request Granted Note that the state diagram assumes that once the bus master has made a request for a transfer, as indicated by Request, then Request remains asserted until the bus master has performed a transfer. As the main bus master state machine operates from the falling edge of the clock, it is necessary to use latched versions of the transfer response signals bwait, berror and blast to control the exit from the ACTIVE state. The reset conditions are not shown on the state diagram and, in a similar manner to the granted state machine, the main bus master state machine has a complex reset term. If agnt is asserted during reset, when nreset is low, the bus master is the default bus master and enters the IDLE state. However, if agnt is not asserted during reset then the bus master enters the IDLE state. 7 The following table indicates the actions that must occur in each state. Name IDLE Description The master does not require the bus and it is not granted. The master does not require the bus, but it has been granted anyway. The master requires the bus, but it has not been granted. Active state when data transfers occur. Exiting this state is dependent on the transfer response. Retract state, where the rest of the elements in the system see the transfer finish, but the bus master is not advanced. Actions Internal btran is Address-only Master clock is enabled Master address bus is tri-stated Internal btran as indicated by master Master clock is enabled Master address bus enable is generated from Granted signal Internal btran is Address-only Master clock is disabled Master address bus is tri-stated Internal btran as indicated by master Master clock enable is derived from BWAIT Master address bus enable is generated from Granted signal Internal btran is Address-only Master clock is disabled Master address bus enable is generated from Granted signal BUSIDLE HOLD ACTIVE RETRACT 8 Bus Interface Bus Interface Timing Diagrams The following diagrams show the timings for the parameters described in this datasheet. For complete timing diagrams, see the "System Architecture" datasheet. Figure 7. ASB Bus Master Non-sequential Transfer System Clock btran1:0] n_tran bprot[1:0] Non-sequential Control tovctin Response bwait_in berror_in blast_in tohctl tisresp tihresp Start of Transfer End of Transfer For the non-sequential transfer shown above, the address and control signals become valid in the system clock high phase before the start of the transfer. An important feature of the AMBA protocol is that it allows for poor output valid times on non-sequential transfers, which is provided through the automatic insertion of a wait state at the start of every non-sequential transfer by the decoder. Figure 8. ASB Bus Master Sequential Transfer System Clock btran1:0] s-tran bprot1:0] Sequential Control tohctl Response bwait_in berror_in blast_in tisresp tihresp Start of Transfer End of Transfer 9 A sequential transfer has different timing parameters for the address and control signal valid times. In a typical bus master, the output valid times for sequential transfers are far better than for non-sequential transfers. The output hold times for address, control and data are identical and independent of the transfer type. The other difference between the sequential and nonsequential transfers is that during a sequential transfer the data may be driven during the first phase of the transfer and hence the data valid parameter is specified from the falling edge of the system clock. Figure 9. ASB Master Address-only Transfer System Clock For an Address-only transfer the address and control signals may be driven in the clock high phase before the start of the transfer, or in the case of bus master hand-over may only be driven during the clock low phase of the transfer itself. The address and control valid timing parameters are only relevant when the Address-only transfer is followed immediately by a sequential transfer and in this case the address and control signals must be driven such that they are valid during the low phase of the Address-only transfer, which in turn means they are valid throughout the clock high phase that precedes the Sequential transfer. btran[1:0] a-tran bprot[1:0] tovctla Control DONE bwait berror blast tisresp tihresp Start of Transfer End of Transfer Figure 10. ASB Bus Master Arbitration and Reset Signals System Clock tihnres nreset_r tisnres agntx tisagnt tihagnt The nreset_r signal may be asserted asynchronously and so there is no setup and hold parameter relating to the assertion of the signal. The AGNT signal, which is returned from the arbiter changes during the low clock phase. 10 Bus Interface Bus Interface Timing Parameters The timing parameters related to an ASB bus master operating in an AMBA system are also shown in textual form in the following two tables. The first details the input signals, while the second details output signals. Table 2. Bus Master Input Timing Parameters Parameter Description nreset de-asserted setup to rising system clock nreset de-asserted hold after falling system clock bwait, berror and blast setup to rising system clock bwait, berror and blast hold after rising system clock agnt setup to rising system clock agnt hold after falling system clock tisnres tihnres tisresp tihresp tisagnt tihagnt Table 3. Bus Master Output Timing Parameters Parameter tovctin tovctla tohctl Description For Non-sequential transfers, bprot[1:0] valid after rising system clock For Address-only transfers, bprot[1:0] valid after falling system clock bprot[1:0] hold after rising system clock 11 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Atmel Rousset Asia Japan Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 literature@atmel.com Web Site BBS http://www.atmel.com 1-(408) 436-4309 (c) Atmel Corporation 2000. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Printed on recycled paper. 1283B-05/00/0M Terms and product names in this document may be trademarks of others. |
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